The present disclosure relates to analog-to-digital (A/D) converters, and more particularly to improvement in throughput of A/D converters.
With recent development of a ubiquitous technology, a radio technology, a high-speed interface technology, etc., there is an urgent need to achieve high performance of A/D converters which convert analog voltage information to a digital value. However, although large-scale integration devices (LSIs) are miniaturized, it is still difficult to improve performance of A/D converters because analog circuits in LSIs generally do not obey Moore's law. To achieve high performance, A/D converters are arranged in parallel and interleave control is performed on a plurality of A/D converters. Such arrangement can improve the throughput of A/D conversion as a whole, even if an operation speed of a single A/D converter is relatively slow.
When paralleling A/D converters, timing skew of interleave control is a critical factor. Thus, the timing skew is digitally compensated for to improve accuracy of conversion. See, e.g., Manar El-Chammas and Boris Murmann, “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC with Background Timing Skew Calibration,” 2010 Symposium on VLSI Circuits/Technical Digest of Technical Papers, pp. 157-158; and Chun-Cheng Huang, Chung-Yi Wang, and Jieh-Tsorng Wu, “A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration,” 2010 Symposium on VLSI Circuits/Technical Digest of Technical Papers, pp. 159-160.
A/D converters operating in parallel require a plurality of sample-and-hold circuits holding an analog voltage which is input to each of the A/D converters. Although high accuracy of these sample-and-hold circuits is required, it is difficult for them to hold an analog voltage with high accuracy when LSIs are further miniaturized or designed to operate at lower voltage levels. Unmatched characteristics of the sample-and-hold circuits in the A/D converters operating in parallel degrade conversion accuracy. Thus, although it is conceivable that the characteristic variations of the sample-and-hold circuits are digitally compensated for by each of the sample-and-hold circuits, it is extremely difficult to additionally compensate for variations of frequency characteristics. That is, characteristic variations of the analog circuits such as the sample-and-hold circuits are a bottleneck in improving performance of the A/D converters arranged in parallel.
Thus, there is a need for an A/D converter having high accuracy and high throughput irrespective of characteristic variations of analog circuits.